• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A search device for obtaining initial synchronization in a CDMA system and a method therefor are provided to correlate a received signal with a value adding 2 PN(Pseudo Noise) codes thereto, and to reduce time for obtaining the initial synchronization in halves, thereby decreasing power consumption. CONSTITUTION: Code generators(111,113) add many PN codes thereto, and output the added PN codes. Despreaders(120,130) multiply an I signal received from an I-channel, a Q signal received from a Q-channel, and the PN codes, respectively, and output the multiplied values. Accumulators accumulate outputted signals of the despreaders(120,130), and output the accumulated values. Squaring units(210,220) square outputted signals of the accumulators, and obtain energy. An adder(230) obtains a sum of energy of the I-channel and energy of the Q-channel by adding the outputted signals of the squaring units(210,220), and outputs the sum. Integrators(140,150) accumulate the outputted signals of the adder(230), and output the accumulated signals.
    公开号:KR20030080139A
    申请号:KR1020020018652
    申请日:2002-04-04
    公开日:2003-10-11
    发明作者:진민호
    申请人:엘지전자 주식회사；
    IPC主号:
    专利说明:

    Searching apparatus and method for initial synchronization acquisition in code division multiple access system {SEARCHER AND METHOD FOR RECOVERING INITIAL CODE SYNCHRONIZATION IN CODE DIVISION MULTIPLE ACCESS}
    [11] The present invention relates to a search apparatus and method for initial synchronization acquisition in a code division multiple access system. In particular, the time required for initial code synchronization acquisition is 1/2 as correlated with a signal received by adding two pseudo noise codes. The present invention relates to a search apparatus and a method for initial synchronization acquisition in a code division multiple access system, which is shortened and implements a multiplier structure by simply shift left and two's complement.
    [12] In general, the pseudo noise code synchronization of a code division multiple access system is largely divided into two processes. After approximating the pseudo noise code delay time of the received signal, the pseudo noise code synchronization tracking loop is used to continuously track the pseudo noise code timing.
    [13] That is, the code searcher adjusts the phase of the pseudo noise code of the receiver so that the error between the pseudo noise code on the transmitting side and the pseudo noise code on the receiving side is within 1/2 chip. This function tracks and maintains precise synchronization, and performs data demodulation function when synchronization between transmitter and receiver is completed.
    [14] 1 is a block diagram showing a configuration of a conventional two-phase shift keyed code searcher, which includes a pseudo noise code generator 11 generating a pseudo noise code as shown therein; Multiplier 12 and integrator 14; A power supply 21 for obtaining energy of the integrated signal; A multiplier 13 and integrator 15 for correlating signals received in the cue-channel; A multiplier 22 for obtaining the energy of the integrated signal; An adder 23 for adding the i-channel energy and the cu-channel energy; And an integrator 31 for integrating the i-channel energy and the cue-channel energy, and a code synchronization acquisition discriminator for determining initial code synchronization acquisition with the integrated energy.
    [15] FIG. 2 is a block diagram showing a conventional quadrature phase shift keying code searcher. The cue channel path is added to the correlator 45 of the eye channel, and the eye channel path is added to the cue channel correlator 46. It is configured as a two-phase shift modulated code searcher, and the conventional code searcher configured as described above is as follows.
    [16] In the code division multiple access system, the received signal and the locally generated code must be synchronized in time to demodulate the code division multiple access signal.
    [17] In order for this synchronization to be obtained as soon as possible, a process of allowing the phase difference between the received code and the generated code to fall within one-half chip is called initial code synchronization acquisition and performs more accurate code synchronization after the initial synchronization acquisition. The process of doing this is called code tracing, and this process is executed by the code tracer.
    [18] The initial code synchronization acquisition process is correlated with the code generated at any time since the receiver cannot know where the code of the received signal is located in time.
    [19] If the code is synchronized, the correlation energy between the received signal and the generated code becomes very large.
    [20] Accordingly, the code searcher compares the correlation energy value with a specific value and determines that the correlation energy value is large.
    [21] If the code is out of sync, this correlation energy value is so small that the code searcher delays the generated signal by one phase or quickly and correlates it with the received signal. This process continues until initial code synchronization is obtained.
    [22] However, in the prior art as described above, the code searcher correlates the code generated in the code generator with the received code to correlate the received code with another code that is delayed when synchronization acquisition fails to determine initial code synchronization acquisition. The code explorer must correlate all codes in the worst case for the initial time synchronization of the code. In this case, the time t required for acquiring initial code synchronization takes as many as the number n of all codes in the time T for at least one code synchronization (t = T × n).
    [23] Accordingly, there is a problem in that it takes a long time to acquire the initial code synchronization in the code searcher.
    [24] Accordingly, the present invention has been made in view of the above problems, and in order to reduce the time taken for initial code synchronization acquisition, the time required for initial code synchronization acquisition is correlated with the received signal plus two pseudo noise codes. The purpose of the present invention is to provide a search apparatus and method for initial synchronization acquisition in a code division multiple access system capable of quickly performing initial code synchronization by implementing a multiplier structure by simply shift left and two's complement. have.
    [1] Figure 1 is a block diagram showing the configuration of a conventional two-phase shift modulation code searcher.
    [2] Figure 2 is a block diagram showing the configuration of a conventional quadrature phase shift modulation code searcher.
    [3] Figure 3 is a block diagram showing the configuration of a two-phase shift modulation code searcher according to the present invention.
    [4] 4 is a block diagram showing the configuration of a quadrature phase shift keying code searcher according to the present invention;
    [5] 5 is a flow chart for explaining the operation of the correlator according to the present invention;
    [6] 6 is a flowchart illustrating a search method for initial synchronization acquisition in a code division multiple access system according to the present invention;
    [7] ** Description of the symbols for the main parts of the drawings **
    [8] 111, 113: code generator 120, 130: multiplier
    [9] 140, 150: integrator 210, 220: square
    [10] 230: adder
    [25] The present invention for achieving the above object, the code generator for adding and outputting a plurality of pseudo noise code; A despreader for multiplying and outputting an i-signal received in an i-channel and a cue signal received in a cue-channel and a pseudo noise code generated by the code generator, respectively; An accumulator for accumulating and outputting a signal output from the despreader; A power squarer that squares an output signal of the accumulator to obtain energy; An adder which adds an output signal of the multiplier to obtain a sum of energy of the i-channel and energy of a cue-channel; And an integrator that accumulates the output signal of the adder and outputs the accumulator to the synchronizer.
    [26] In addition, correlating the received signal with the sum of two locally generated pseudo noise codes and determining that initial code synchronization is obtained if the correlation value is greater than a specific value; When the initial code synchronization is obtained, the received signal is synchronized with one of two locally generated pseudo noise codes, and thus, determining which code of the two codes is synchronized and finishing the initial code synchronization acquisition. It is characterized in that the operation.
    [27] Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.
    [28] 3 is a block diagram showing the configuration of a two-phase shift modulation code searcher according to the present invention. As shown in FIG. 3, a pseudo noise code generated by the first code generator 113 and the second code generator 111 is added. A code generator for outputting; A first multiplier (120) for multiplying and outputting an eye signal received in an I-channel and a pseudo noise code generated by the code generator; A first integrator (140) for integrating and outputting the signal output from the first multiplier (120); A first multiplier (210) for obtaining energy by squaring an output signal of the first integrator (140); A second multiplier (130) for multiplying a signal received in a cue-channel by a pseudo noise code generated by the code generator; A second integrator (150) for integrating and outputting the signal output from the second multiplier (130); A second multiplier (220) for obtaining energy by squaring an output signal of the second integrator (150); An adder 230 for adding and outputting the output signals of the first and second power generators 210 and 220 to obtain the sum of the energy of the i-channel and the energy of the cue-channel; And a third integrator 310 which integrates the output signal of the adder 230 and outputs the integrated signal to the synchronizer.
    [29] 4 is a block diagram showing a configuration of a quadrature phase shift modulation code searcher according to the present invention, and outputs by adding a pseudo noise code generated by the first eye code generator 421 and the second eye code generator 423. An eye code generator; A cue code generator for adding and outputting a pseudo noise code generated by the first cue code generator 441 and the second cue code generator 443; A first multiplier (450) for multiplying a pseudo noise code output from the eye code generator and an eye signal received in an eye channel; A second multiplier (470) for multiplying a pseudo noise code output from the cue code generator and an eye signal received in the i-channel; A fourth multiplier (460) for outputting the pseudo noise code output from the eye code generator by multiplying the pseudo noise code inverted by the third multiplier (430) and the cue signal received in the cue-channel; A fifth multiplier 480 for multiplying and outputting a pseudo noise code output from the cue code generator and a cue signal received in a cue-channel; A first adder (490) for adding the output signal of the first multiplier (450) and the output signal of the fifth multiplier (480); A second adder (500) for adding the output signal of the second multiplier (470) and the output signal of the fourth multiplier (460); A first integrator 510 for integrating and outputting the output signal of the first adder 490; A first multiplier (610) for obtaining the energy of the integrated signal by squaring the output signal of the first integrator (510); A second integrator 520 for integrating and outputting the output signal of the second adder 500; A second multiplier (620) for obtaining the energy of the integrated signal by squaring the output signal of the second integrator (520); A third adder (630) for adding and outputting the output signal of the first multiplier (610) and the output signal of the second multiplier (620); An embodiment of the present invention will be described as consisting of a third integrator 710 for integrating and outputting the output signal of the third adder.
    [30] The present invention obtains initial code synchronization by correlating a received signal with a pseudo noise signal obtained by adding two or more locally generated codes to shorten the initial code synchronization acquisition time.
    [31] In this method, even if only one pseudo noise code of locally generated code is synchronized, the correlation value becomes very large.
    [32] Therefore, this embodiment has an initial acquisition speed of almost twice that of the method of locally generating one pseudo noise code to acquire initial code synchronization.
    [33] Also, in the above embodiment, only two pseudo noise codes generated locally are applied, but in another embodiment, several pseudo noise codes may be applied.
    [34] Here, the code searcher that correlates by adding two locally generated pseudo-noise codes can easily implement a multiplier, which has many advantages in the implementation of the code searcher.
    [35] The sum of the two pseudo-noise codes is only -2, 0, +2, so that the multiplier can be easily implemented as a shift register, and a multiplier can be implemented that produces fast multiplication results.
    [36] As shown in FIG. 5, when the sum of two pseudo noise codes is 0, the algorithm outputs a received signal as 0 (S1, S2). If +2, the shifted signal is simply shifted and output. In the case of -2, the shift left and the binary complement are output (S5).
    [37] 6 is an operation flowchart of a search method for initial synchronization acquisition in a code division multiple access system according to the present invention. If a correlation value is greater than a specific value by correlating a received signal with a sum of two locally generated pseudo noise codes, FIG. Determining that initial code synchronization has been acquired (S11 to S13); When the initial code synchronization is obtained, the received signal is in synchronization with one of two locally generated pseudo noise codes, and thus, determining which code of the two codes is synchronized and finishing the initial code synchronization acquisition ( S21 ~ S23) is described as follows.
    [38] The code searcher combines two locally generated pseudo-noise codes and compares them with a specified value and compares them with a specific value. If the correlation value is smaller than the specified value, the code searcher delays or accelerates the two pseudo-noise codes again. Correlates with
    [39] On the contrary, if the correlation value is greater than a specific value, the code searcher correlates with the received signal using only one code of two codes. When judged, it is determined to be in synchronization with the rest of the code.
    [40] Thereafter, a multi-dwell process for more accurately determining an initial code synchronization acquisition may be performed in some cases.
    [41] As described in detail above, the present invention correlates the received signal with the value of two pseudo noise codes to reduce the time required for acquiring the initial code synchronization by 1/2 to reduce power consumption in the logic implementation of the code searcher. By implementing the structure of the multiplier by simply shift left and two's complement, the area required for implementing the logic of the code explorer can be reduced.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] A code generator for adding and outputting a plurality of pseudo noise codes; A despreader for multiplying and outputting an i-signal received in an i-channel and a cue signal received in a cue-channel and a pseudo noise code generated by the code generator, respectively; An accumulator for accumulating and outputting a signal output from the despreader; A power squarer that squares an output signal of the accumulator to obtain energy; An adder which adds an output signal of the multiplier to obtain a sum of energy of the i-channel and energy of a cue-channel; And an integrator configured to accumulate an output signal of the adder and output the accumulator output signal to a synchronization discriminator.
    [2" claim-type="Currently amended] 2. The apparatus of claim 1, wherein the despreader comprises: a first multiplier for multiplying and outputting an eye signal received in an i-channel and a pseudo noise code generated in a code generator; And a second multiplier for multiplying and outputting a cue signal received from a cue channel and a pseudo noise code generated by the code generator.
    [3" claim-type="Currently amended] 2. The apparatus of claim 1, wherein the code generator comprises: an eye code generator for adding a plurality of pseudo noise codes corresponding to an eye channel to the despreader; A search apparatus for initial synchronization acquisition in a code division multiple access system, comprising: a cue code generator for adding a plurality of pseudo noise codes corresponding to a cue channel and outputting the despreader.
    [4" claim-type="Currently amended] 4. The apparatus of claim 3, wherein the despreader comprises: a first multiplier for multiplying a pseudo noise code output from an eye code generator and an eye signal received in an eye channel; A second multiplier for multiplying a pseudo noise code output from the cue code generator and an eye signal received in the eye channel; A fourth multiplier for multiplying and outputting a pseudo noise code output from the eye code generator by a cue signal received in a cue channel and a pseudo noise code inverted by a third multiplier; A fifth multiplier configured to multiply and output a pseudo noise code output from the cue code generator and a cue signal received in a cue-channel; A first adder configured to output an output signal of the first multiplier and an output signal of the fifth multiplier; And a second adder configured to add an output signal of the second multiplier and an output signal of the fourth multiplier to output the second multiplier.
    [5" claim-type="Currently amended] Correlating the received signal with the sum of two locally generated pseudo noise codes and determining that initial code synchronization has been acquired if the correlation value is greater than a specified value; When acquiring the initial code synchronization, it is determined to which of the two pseudo-noise codes are synchronized again to complete the initial code synchronization acquisition search for initial synchronization acquisition in the code division multiple access system, characterized in that Way.
    [6" claim-type="Currently amended] 6. The method of claim 5, wherein if the sum of the two pseudo noise codes is 0, the received signal is outputted as 0. If +2, the received signal is simply shifted left and outputted. A search method for initial synchronization acquisition in a code division multiple access system, characterized in that it is configured to output by complementary complement.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-04-04|Application filed by 엘지전자 주식회사
    2002-04-04|Priority to KR1020020018652A
    2003-10-11|Publication of KR20030080139A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020018652A|KR20030080139A|2002-04-04|2002-04-04|Searcher and method for recovering initial code synchronization in code division multiple access|
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